By Jens Eickhoff (auth.), Jens Eickhoff (eds.)
This e-book describes the improvement and layout of a different mixed facts and gear administration infrastructure The use in small satellites offers a few specific necessities to the platforms like strength failure robustness and dealing with of other different types of exterior analog and electronic interfaces. those standards bring about a practical merge among On Board computing device and the satellite's energy keep watch over and Distribution Unit, which ends up in a truly leading edge layout or even a patent association. This publication presents approach engineers and college scholars with the technical wisdom as combine among technical brochure and a person guide.
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Extra info for A Combined Data and Power Management Infrastructure: For Small Satellites
SpaceWire Clock: The SpaceWire clock as already cited is 10 MHz. 8 DSU/Ethernet Interface Card (DEI) For debug and test of the OBC Processor-Boards—both EM and FM models—a small PCB card was designed by Aeroflex Colorado Springs to interface to the LEON3FT DSU and Ethernet ports respectively. Details on this card can be found in Sect. 1. 2 The OBC Processor-Boards 41 The Ethernet interface on the LEON3FT is implemented by routing the signals from the LEON3FT to the 44 pin D-sub connector. During debug the user will use the DSU/Ethernet Interface card to implement the Ethernet connection.
In any case of reconfiguration of the Data Handling and Operations (DH/OPS) subsystem or of the power subsystem, essential control functions of the satellite are at least blocked or non-operational for a limited time which will degrade the spacecraft attitude and power control. So besides pure failure management in form of switchover to a redundant unit, the FDIR system must assure shutdown of non essential power loads (payloads, thermal consumers) and must assure bringing back the satellite into a safe-mode configuration.
The on chip LEON3FT EDAC function has been implemented on the SBC for both the volatile and the non-volatile memory spaces. The following section discuss in more detail all of the interfaces on the SBC. A top level functional diagram of the OBC flight board is shown in Fig. 5 which provides a graphical view of the overall design of the OBC ProcessorBoard. UT699 LEON3 SLEEP Bits Spw2 10 Mbs Spw3 10 Mbs Spw4 10 Mbs Address /Data 8MB EDAC SRAM SRAM CE Leon 3 Addr 20 to 22 RAMS and ROMS Signals 4MB EDAC NVMEM UT6325 FPGA Dedicated SpaceWire Buses Spw1 10 Mbs RS-422 Ethernet One Second Pulse NVMEM CE Fig.
A Combined Data and Power Management Infrastructure: For Small Satellites by Jens Eickhoff (auth.), Jens Eickhoff (eds.)